FIG. 9 shows a configuration of a delay circuit according to a conventional art. An input signal line IN is connected to gates of a p-channel MOS transistor 901 and an n-channel MOS transistor 902. A source of the transistor 901 is connected to a power supply potential, and a source of the transistor 902 is connected to a ground potential. A resistor 903 is connected between drains of the transistors 901 and 902. They constitute a first-stage inverter.
An output of the first-stage inverter is the drain of the transistor 901, which is connected to an input signal line of a second-stage inverter. An output of the second-stage inverter is a drain of a transistor 902, which is connected to an input signal line of a third-stage inverter. An output of the third-stage inverter is a drain of a transistor 901, which is connected to an input signal line of an inverter 905. Capacitors 904 are connected to output signal lines of the first-stage to third-stage inverters respectively. A delay signal of an input signal inputted to the input signal line IN is outputted to an output signal line OUT of the inverter 905.
The resistors 903 and the capacitors 904 are capable of adjusting a delay time of the delay signal outputted from the output signal line OUT. The resistors 903 of the first-stage and third-stage inverters are resistors for adjusting a delay time at the time when the input signal inputted to the input signal line IN rises. The resistor 903 of the second-stage inverter is a resistor for adjusting a delay time at the time when the input signal inputted to the input signal line IN drops.
The delay time of the delay circuit has power supply voltage dependency. The higher the power supply voltage is, the shorter the delay time becomes. Specifically, when the power supply voltage becomes higher, a larger electric current flows between the sources and drains of the transistor 901 and 902, so that the switching speed of the transistors 901 and 902 becomes higher. As a result, the delay time becomes shorter.
The power supply voltage has been on the decrease in recent years. The lowered power supply voltage causes the delay time to be longer. Further, with a power supply voltage in a lower voltage range, the delay time tends to become still longer due to the influence of a threshold voltage of the transistors 901 and 902.
In a RAM such as a DRAM or a pseudo SRAM, a predetermined length of time or longer is constantly necessary for the restore time of memory cells. In a case where the restore time is set in a delay circuit using a high power supply voltage, the use of a low-power supply voltage results in an excessively long delay time if the power supply voltage dependency of the delay time is too large. The excessively long delay time results in an excessively long access time of the RAM determined by the low power supply voltage. This means that characteristics of the RAM are determined by the delay time of the delay circuit.